1. Field of the Invention
The present invention relates generally to non-volatile memory cells.
2. Description of the Related Art
Memory cells comprising semiconductor components which are operated as dynamic or static memories generally loose the stored information after the supply voltage has been switched off. In the case of a spontaneous voltage failure, all data stored in these memories are erased.
In the case of memory cell arrangements which are built up from dynamic single-transistor cells, the additional disadvantage is that a refresh must be carried out at regular time intervals for compensating for the charge drained by leakage currents. This increases power consumption and circuit complexity.
Furthermore, dynamic memories are sensitive against alpha radiation. This produces error bits.
It is known (see for example S. M. Sze, Semiconductor Devices, John Wiley & Sons 1985, p. 490), to use so-called electrically programmable memories (EPROM) or electrically programmable and erasable memories (EEPROM) for permanent storage. In these non-volatile memories, the load is retained when the voltage supply is switched off. In these memories, the information is stored with the aid of the charging-up of a floating gate by the injection of hot charge carriers or Fowler-Nordheim tunnel current or by charging up impurity traps and dielectric boundary layers (NMOS transistors). In this arrangement, the floating gate or the impurity traps are surrounded by a high-quality insulator so that there is virtually no charge drainage.
A disadvantage of these memories is that the write process takes place with time constants in the millisecond range, that is to say is relatively slow. A further disadvantage consists in that the high-quality insulator becomes fatigued after about 10.sup.3 to 10.sup.6 write cycles. After that, no further permanent charge storage can then be carried out.